1. Field of the Invention
The present invention relates to a data-rewritable non-volatile semiconductor memory device.
2. Description of the Related Art
Data-rewritable non-volatile semiconductor memory devices, for example, EEPROMs and flash ROMs, have widely been used as storage devices for various electronic apparatuses. In the non-volatile semiconductor memory device, data is rewritable by injection of electrons into a float gate of a preset MOS transistor as a one constituent of a memory cell and release of electrons from the floating gate. In a data reading operation, the operating current of the preset MOS transistor, which is based on the on-off state of the preset MOS transistor, determines the operating current of a selected memory cell. The on-off state of the preset MOS transistor is changed according to the magnitude of a potential level at the floating gate of the selected memory cell relative to a predetermined reference potential. Data corresponding to the writing condition of the memory cell is output and read from a sense amplifier circuit, based on the determined operating current of the memory cell.
In the conventional non-volatile semiconductor memory device, the state of injection of electrons into the floating gate and the state of release of electrons from the floating gate are not generally fixed but are significantly varied. This causes the varying potential level at the floating gate in the data reading operation and results in a significant variation in operating current of the memory cell.
The fluctuation range of the potential level at the floating gate relative to the predetermined reference potential, which depends upon the variation of the data writing condition, is reduced by repeated data writing and data erasing operations.
In the conventional non-volatile semiconductor memory device, the circuit structure is designed with a sufficient margin to ensure a sufficiently large operating current of the memory cell. This aims to stably read data from the memory cell even in a minimum allowable fluctuation range of the potential level at the floating gate relative to the reference potential. Such tactic of the circuit design is, however, not desirable for the optimized circuit structure.
One example of the prior art technique is disclosed in U.S. Pat. No. 5,331,590.